(1) Field of the Invention
This invention relates to a method of making, and the resultant structure for, a DRAM (Dynamic Random Access Memory) cell, and more particularly to a method of making, and the resultant structure of, a DRAM stack capacitor.
(2) Description of the Related Art
A typical DRAM cell consists of a single transistor and a storage capacitor. Digital information is stored in the capacitor and accessed through the transistor, by way of addressing the desired memory cell, which is connected with other such cells through an array of bit lines and word lines. In order to construct high density DRAMs in a reasonably sized chip area, both the transistor and capacitor elements must occupy less lateral space in each memory cell than in the previous generation DRAM designs. As DRAMs are scaled down in dimensions, there is a continuous challenge to maintain a sufficiently high stored charge per capacitor unit area. Efforts to increase capacitance without increasing the planar area of the capacitor have been concentrated on building three dimensional capacitor structures, which increase the capacitor surface area. Thus cell structures have had to change from the conventional planar-type capacitors to either trench capacitors or stack capacitors, in particular at densities above 4 Mbit.
When the stack capacitor approach is used, in order to maintain sufficient capacitance the storage node must have a large surface area, and consequently must be formed significantly above the surface of the substrate in which the DRAM cell is formed, thus leading to topological problems in the formation of subsequent layers.
In the prior art DRAM cell of FIG. 1, an FET (Field Effect Transistor) is shown on each side of field oxide 12, on silicon substrate 2, and consists of gate electrode 14 and active regions 4. Word lines 6 are formed to connect memory cells together, and are commonly formed on field oxide 12. An insulating layer 16 is deposited and patterned to form cell contacts 10 to provide the capacitor to FET contact. The bottom electrode 11 of the capacitor is shown, and the capacitor would be completed by adding a dielectric and top electrode to the FIG. 1 structure. In order to provide the large surface area needed, or to increase the capacitance, the capacitor must be formed at a significant height above the substrate.